Closing the Gap Between Specification and Programming: VDM++ and Scala

We argue that a modern programming language such as Scala offers a level of succinctness, which makes it suitable for program and systems specification as well as for high-level programming. We illustrate this by comparing the language with the Vdm specification language. The comparison also identifies areas where Scala perhaps could be improved, inspired by Vdm. We furthermore illustrate Scala’s potential as a specification language by augmenting it with a combination of parameterized state machines and temporal logic, defined as a library, thereby forming an expressive but simple runtime verification framework.